1. Field of the Invention
This invention relates in general to clock signal generation, and more particularly to a method and apparatus for regulating the duty cycle of a digital clock signal derived from an oscillator signal.
2. Description of Related Art
Global communications continues to demonstrate rapid growth rates. As more people become accustomed to the convenience of electronic mail, web-based facsimile transmission, electronic commerce, telecommuting and high-speed Internet access, the demand on the telecommunications industry to provide adequate bandwidth to provide this type of service also increases. The growth in the number of people using electronic communications will only increase as the price of Internet access and Internet access devices such as personal digital assistants (PDAs), computers, etc. decreases.
Today, copper telephone lines service almost all voice traffic and most of the Internet traffic. However, as content rich applications continue to grow, both public and private copper access networks are being challenged. The local portion of the enterprise becomes a major challenge for access providers. To take advantage of the increasingly popular innovations in telecommunications technology, additional telephone lines are being installed in private residences and businesses.
Although analog modems have managed to stretch their potential speed to 56 kilobits per second (kbps), small-office/home-office (SOHO) customers need far greater Internet bandwidth to accommodate multimedia applications ranging form three-dimensional web sites to video conferencing. Analog modems cannot deliver the necessary bandwidth and, therefore, have reached the end of their usefulness.
In response to these developments, communications companies are responding with a variety of digital access solutions, all variants of Digital Subscriber Line (DSL) technology. These DSL technologies differ dramatically in their abilities to address major SOHO applications and the requirements of telephone companies.
DSL technologies are transport mechanisms for delivering high-bandwidth digital data services via twisted-pair copper wires. These copper wires provide the cabling between the telephone company""s central offices and subscribers. DSL technology is a copper loop transmission technology that solves the bottleneck problem often associated with the last mile between Network Service Providers and the users of those network services. DSL technology achieves broadband speeds over ordinary phone wire. While DSL technology offers dramatic speed improvements (up to 7+ Mbps) compared to other network access methods, the real strength of DSL-based services lies in the opportunities driven by multimedia applications required by today""s network users, performance and reliability and economics.
Without such transport mechanisms, subscribers would have to rely on T1 (1.5 Mbps) or E1 (2.0 Mbps) service, which requires the phone company to install expensive new cabling to every location that wants high-speed digital service. The installation costs make T1/E1 service expensive.
The original DSL service was ISDN DSL (ISDL), which was defined in the late 1980s. ISDL provides 160 kbps rates over a single twisted-pair at ranges up to 18,000 feet from the telephone company""s central office. While this service has been deployed in many homes and small businesses around the world, the demands of multimedia applications are already challenging IDSL""s bandwidth.
Asymmetric Digital Service Line (ADSL) is currently being embraced by residential web surfers for its ability to quickly download music and video files. ADSL refers to modem technology that transforms twisted copper pair (ordinary phone lines) into a pipeline for ultra fast Internet access. As the name suggests, ADSL is not asynchronous transmission, but rather asymmetric digital transmission, i.e., ADSL transmits more than 6 Mbps (optionally up to 8 Mbps) to a subscriber, and as much as 640 kbps (optionally up to 1 Mbps) in the other direction.
ADSL has the ability to increase normal phone line capacity by 99% via a digital coding technique. This extra capacity means that one could simultaneously assess the World Wide Web and use the telephone or send a fax. A user of this technology could have uninterrupted Internet access that is always on-line. This technology also has the potential to be a cost-effective solution for residential customers, telecommuters and small business.
Still, there is a need for symmetric high-speed connection. For example, small businesses have become increasingly dependent on sophisticated voice and data products and services for competing against larger corporations. Until now, the cost of providing small businesses with professional telephony and data services was prohibitive. However, integrated access and virtual public branch exchanges (PBXs) are providing small businesses with voice mail, high-speed Internet access, multiple business lines and sufficient capabilities for telecommuters.
As mentioned above, symmetric services were traditionally delivered by T1 and E1 lines. Within the DSL family, HDSL has long been used to provision T1 lines because its long reach requires regeneration-signal boosting only every 12,000 feet, compared with every 4,000 feet for other T1 provisioning techniques. In fact, HDSL""s ability to simplify and cheapen T1 deployment has made HDSL by far the most established of the DSL technology family.
As an inexpensive and flexible replacement for leased T1 lines, the HDSL2 standards are eagerly awaited by the DSL industry. HDSL2 replaces the aging HDSL standard that required two copper pairs. HDSL2 uses only one copper pair and is potentially rate adjustable. HDSL2, which is being developed within the framework of the American National Standards Institute (ANSI, New York), promises to make HDSL more compelling in two ways. While HDSL was a proprietary technique, i.e., modems at the central office (CO) and the customer premises had to come from the same vendor, HDSL2 will be an interoperable standard in which modems can be mixed. Perhaps the biggest selling point of HDSL2, however, is that it can use one pair of copper wires instead of HDSL""s two. Network service providers thus have a choice. HDSL and one-pair HDSL2 have about the same reach, while two-pair HDSL2 adds as much as another 4,000 feet of reach, depending on the gauge of copper and other conditions. Hoping to propel the new DSL technology into the business arena, eight chip makers and OEMs have formed a consortium for the HDSL2 standard.
A typical HDSL2 transceiver transmit path includes a framer, a data pump with an analog interface for coupling to the twisted-pair line. In the transmit function, the framer accepts a digital signal and outputs to the data pump a serial digital signal that includes the data payload plus an HDSL2 overhead. In the receive function, the framer receives HDSL frames from the data pump.
The data pump includes a transceiver and an analog front end for receiving the HDSL frames serially from the framer. The transceiver converts the HDSL frames into a transmit signal by first converting the HDSL frames into symbols. Typically, a modulator, such as a trellis code modulator (TCM) encodes the symbols into a pulse amplitude modulation (PAM) signal. The signal is further processed to condition and filter the PAM signal. The analog front end provides pulse shaping to analog signals. This process is reversed in the receive channel with echo cancellation provided to cancel most of the echoed transmit signal.
As mentioned, the analog front end includes a transmit and a receive channel. In the transmit channel, the analog front end receives a pulse width modulated signal stream from the transceiver. A switched capacitor circuit filter shapes the transmitted signal to meet specific spectral templates. The receive channel consists of an automatic gain control (AGC) stage and an analog-to-digital (A/D) converter. The AGC stage sets the amplitude to the optimum level to prevent saturation of the A/D converter.
Switched-capacitor circuits are needed in communication applications to implement accurate on-chip active filters. Switched-capacitor circuits are also often implemented in high linearity A/D and digital-to-analog (D/A) converters, and have also found their place in precision sample and hold circuits as well as sigma-delta modulation circuits. These switched-capacitor circuits therefore are very beneficial in xDSL environments such as the HDSL2 environment, since filtering, sample/hold, A/D and D/A conversion and modulation are common elements of HDSL transceivers.
Precise operation of switched-capacitor circuits requires precise control of the timing of clock signals used, for example, in sample and hold operations. Insufficient settling of sampled/held signals leads to nonlinearities in the output signals. Insufficient settling of sampled/held signals can occur due to bandwidth limitations of the operational amplifiers used in the system, and can also occur where the timing available to settle varies from chip-to-chip and may not end up with the appropriate settling time. The xe2x80x9ctimingxe2x80x9d is provided by clock signals generated by some sort of clock sourcing device. Therefore, precise timing control of the clock timing is desired.
A traditional manner of guaranteeing a precise 50% duty cycle is to generate the original clock signal at twice the required frequency (2xc3x97 clock signal), and divide this clock signal by two using a digital divide-by-2 frequency divider to arrive at the desired frequency (1xc3x97 clock signal). The frequency divider triggers on the rising (or alternatively falling) edge of the 2xc3x97 original clock, and the division generates the 50% duty cycle 1xc3x97 clock signal. Where the 1xc3x97 clock signal itself is already at a very high frequency and is to be generated using an external crystal oscillator, it may become impractical and cost prohibitive to generate a 2xc3x97 clock signal where only half of its frequency will be used due to the subsequent division, all merely for the purpose of obtaining a more precise 50% duty cycle. Crystal oscillators generally increase in cost as the frequency rises, and can become relatively expensive at very high frequencies. Further, crystal oscillators are more difficult to operate in the fundamental mode of oscillation at very high frequencies. For at least these reasons, it is not desirable to generate accurate 50% duty cycles for clock signals using the technique of doubling the original clock frequency and dividing it down to the desired frequency.
It can be seen then that there is a need for a method and apparatus for creating very accurate 50% duty cycle clock signals, while avoiding the need to manipulate the frequency of the original clock signal. There is also a need for such a method and apparatus that is cost-effective and resource-efficient. The present invention provides a solution to these and other shortcomings of the prior art, and offers additional advantages over the prior art.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for regulating the duty cycle of a digital clock signal.
A method in accordance with the principles of the present invention includes a manner of regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.
In accordance with another embodiment of the invention, a method is provided for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. When the digital clock signal has an actual duty cycle of less than 50%, the DC-biased oscillator signal is sliced at a voltage below its DC component to effectively increase the DC component of the digital clock signal until the digital clock signal has a 50% duty cycle. Alternatively, when the digital clock signal has an actual duty cycle of greater than 50%, the DC-biased oscillator signal is sliced at a voltage above its DC component to effectively decrease the DC component of the digital clock signal until the digital clock signal has a 50% duty cycle.
Another aspect of the present invention provides an apparatus to regulate the duty cycle of a digital clock signal. The apparatus includes a DC referencing circuit to reference an input oscillator signal to a predetermined voltage to create a DC-shifted oscillator signal. A slicer is also provided, which includes a first input coupled to the DC referencing circuit to receive the DC-shifted oscillator signal and a second input coupled to receive a threshold voltage. The slicer further includes an output to supply the digital clock signal having a duty cycle proportional to a difference between a DC component of the digital clock signal and a DC component of the DC-shifted oscillator signal. The apparatus also includes a feedback circuit coupled between the output of the slicer and the second input, so that the DC component of the digital clock signal provides the threshold voltage at the second input of the slicer.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention and its advantages, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.